1. Field of the Invention
This invention relates to a semiconductor device having a wiring substrate and a plurality of semiconductor chips stacked thereon and further relates to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
In recent years, following the reduction in size and thickness, the increase in capacity, and so on of semiconductor devices, it has become necessary to stack semiconductor chips in multi-stages and thus the reduction in thickness of semiconductor chips has been advanced. A related semiconductor device is described, for example, in Japanese Unexamined Patent Application Publication (JP-A) No. 2002-261233 (Patent Document 1). This semiconductor device is configured such that a lower-side semiconductor chip is mounted on a wiring substrate and an upper-side semiconductor chip is mounted on the lower-side semiconductor chip through a spacer.
However, in the case where an electrode pad is disposed at a portion, whose lower surface is not supported, of the upper-side semiconductor chip as in the semiconductor device described in Patent Document 1, there has been a problem that the upper-side semiconductor chip is broken due to pressure contact of a bonding tool when wire-bonding the electrode pad.
In view of this, as a technique for wire-bonding an electrode pad provided at a protruding portion of a semiconductor chip as described above, there has been proposed, for example, Japanese Unexamined Patent Application Publication (JP-A) No. 2000-299431 (Patent Document 2) or Japanese Unexamined Patent Application Publication (JP-A) No. 2005-197491 (Patent Document 3). Patent Document 2 or 3 is only applicable to the case where an upper-side semiconductor chip stacked on a lower-side semiconductor chip disposed on a wiring substrate has a chip size greater than that of the lower-side semiconductor chip.
Specifically, a semiconductor device described in Patent Document 2 is configured such that when flip-chip bonding a lower-side semiconductor chip to a wiring substrate through an anisotropic conductive adhesive, part of the adhesive is forced out from under the lower-side semiconductor chip to form a support portion by the forced-out adhesive and an upper-side semiconductor chip is mounted on the support portion and the lower-side semiconductor chip.
However, in the semiconductor device described in Patent Document 2, since the adhesive is forced out around the lower-side semiconductor chip to form the support portion by the forced-out adhesive, the amount of the adhesive increases for ensuring the height of the support portion. Therefore, there is a possibility that the adhesive spreads toward the outer edge of the wiring substrate to cover connection pads of the wiring substrate to be connected to the upper-side semiconductor chip. Further, since it is configured that the upper-side semiconductor chip is mounted on the back surface of the flip-chip mounted lower-side semiconductor chip and the support portion provided on the wiring substrate around the lower-side semiconductor chip, it is difficult to apply the configuration of Patent Document 2 to a semiconductor chip mounted in a third or subsequent stage.
On the other hand, a semiconductor device described in Patent Document 3 is configured such that a lower-side semiconductor chip is flip-chip bonded to a wiring substrate and an upper-side semiconductor chip is stacked on the lower-side semiconductor chip, wherein the upper-side semiconductor chip has a protruding portion protruding from the outer edge of the lower-side semiconductor chip and a convex support portion is provided on the surface of the wiring substrate, thereby supporting the protruding portion of the upper-side semiconductor chip by the support portion.
However, in the semiconductor device described in Patent Document 3, since it is configured that the support portion is provided on the surface of the wiring substrate, it is difficult to apply the configuration of Patent Document 3 to a semiconductor chip mounted in a third or subsequent stage. For example, if attempting to apply the configuration to the third-stage semiconductor chip, it is necessary to provide a support portion on the wiring substrate around the second-stage semiconductor chip so that the package size increases. Further, it is also necessary to increase the height of the support portion for the third-stage semiconductor chip and thus the package thickness also increases. Further, the chip size of the third-stage semiconductor chip is subjected to a limitation by the distance between the outer edge of the second-stage semiconductor chip and the support portion for the third-stage semiconductor chip. Further, since it is configured that the support portion is formed on the surface of the wiring substrate to directly support the upper-side semiconductor chip, there is a possibility of occurrence of a difference in height between the lower-side semiconductor chip and the support portion and, if the upper-side semiconductor chip is thin enough, there is even a possibility of occurrence of a crack therein due to this difference in height.